Cmos Vlsi Chip of Network of Synchronised Oscillators: Functional Tests Results
نویسندگان
چکیده
This paper presents functional tests results of CMOS VLSI ASIC integrated circuit, which implements a network of synchronised oscillators. The network chip architecture was briefly described. This circuit was designed for segmentation of binary images, which is an important issue in biomedical image analysis. The hardware realisation of oscillator network provides much faster image segmentation compared to computer simulation techniques. Oscillators free frequency tuning idea and procedure have been proposed. Oscillators tunings allowed for segmentation of longer chain objects inputted into synchronised oscillators network chip. Segmentation results of sample binary image obtained using oscillator network chip have been presented and discussed.
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